In applications such as, for example, infrared detector arrays, it is desirable to handle cell address data at very fast rates, in various sequences, and for arrays of different sizes and configurations, with a minimum of hardware. Address manipulation conventionally involves the use of digital comparators which continually compare addresses appearing on an address bus with pre-stored addresses at which certain actions are to be taken.
Conventional comparators for large arrays typically involve many integrated circuit chips, sometimes require hardware changes to accommodate different references for different arrays, and are comparatively slow because each address needs to be loaded into the comparator, compared, and an output generated in separate operational cycles.
Prior art in this field is as follows: U.S. Pat. No. 4,031,511 to Britton, which shows a CMOS comparator made up of discrete components and integrated circuits; U.S. Pat. No. 4,225,849 to Lai, which discloses a tree-type comparators; U.S. Pat. No. 4,495,590 to Mitchell, Jr., which describes a one-time programmable solid state logic device; U.S. Pat. No. 4,536,738 to Huse et al., which describes a macro cell arrangement for programmable array logic; U.S. Pat. No. 4,721,868 to Cornell et al., which shows a scheme for time multiplexing of programmable array logic inputs; U.S. Pat. No. 4,742,252 to Agrawal, which discloses a programmable logic device; U.S. Pat. No. 4,752,763 to Hoffman, which discusses an emitter coupled logic device comparator; U.S. Pat. No. 4,758,747 to Young et al., which describes a buried register circuit; and U.S. Pat. No. 4,760,374 to Moller, which shows an emitter coupled logic bounds checker. SUMMARY OF THE INVENTION
The present invention provides a versatile, easily programmable comparator which is constructed entirely by software from a standard off-the-shelf generic array logic device such as a GAL.RTM. 39V18 chip manufactured by Lattice Semiconductor Corporation of Portland, Oreg. Generic array logic typically provides a set of flip-flops and associated gates which can be selectively and modifiably interconnected by software in the form of a JEDEC file.
In the case of the above-mentioned 39V18 chip, the eighteen registers of the chip can be programmed, in accordance with the invention, to provide a 17-bit comparison in a single chip, without using any external registers. An eighteenth bit is available for the cascading of other chips. In practical terms, this means that address matrixes as large as 360.times.360 can be compared by a single chip.
In addition, the comparator of this invention needs no loading of addresses to be compared; whenever the address data on the bus matches an internally stored address, a "match" output is instantly produced and maintained as long as the matching address is on the bus. Also, the device is self-testing: whenever a new reference address is clocked into the comparator, the presence of the reference address on the bus as it is being clocked into storage produces a "match" output if the comparator is functioning properly.